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91400 rm (im) hs no.6693-1/20 ver.1.01 n1798 preliminary overview the lc863232/28/24/20/16a are 8-bit single chip microcontrollers with the following on-chip functional blocks: - cpu : operable at a minimum bus cycle time of 0.424 s - on-chip rom capacity program rom : 32k/28k/24k/20k/16k bytes cgrom : 16k bytes - on-chip ram capacity : 512 bytes - osd ram : 352 9 bits - closed-caption tv controller and the on-screen display controller - closed-caption data slicer - four channels 8-bit ad converter - three channels 7-bit pwm - two 16-bit timer/counters, 14-bit base timer - 8-bit synchronous serial interface circuit - iic-bus compliant serial interface circuit (multi-master type) - rom correction function - 16-source 10-vectored interrupt system - integrated system clock generator and display clock generator only one x ? tal oscillator (32.768khz) for pll reference is used for both generators tv control and the closed caption function all of the above functions are fabricated on a single chip 8-bit single chip microcontroller lc863232/28/24/20/16a ordering number : enn*6693 cmos ic
lc863232/28/24/20/16a no.6693-2/20 features (1) read-only memory (rom) : 32768 8 bits / 28672 8 bits / 24576 8 bits 20480 8 bits / 16384 8 bits for program 16128 8 bits for cgrom (2) random access memory (ram) : 512 8 bits (including 128 bytes for rom correction function) 352 9 bits (for crt display) (3) osd functions - screen display : 36 characters 16 lines (by software) - ram : 352 words (9 bits per word) display area : 36 words 8 lines control area : 8 words 8 lines - characters up to 252 kinds of 16 32 dot character fonts (4 characters including 1 test character are not programmable) each font can be divided into two parts and used as two fonts : a 16 17 dot and 8 9 dot character font at least 111 characters need to be divide to display the caption fonts. - various character attributes character colors : 16 colors character background colors : 16 colors fringe / shadow colors : 16 colors full screen colors : 16colors rounding underline italic character (slanting) - attribute can be changed without spacing - vertical display start line number can be set for each row independently (rows can be overlapped) - horizontal display start position can be set for each row independently - horizontal pitch (bit 9 - 16) *1 and vertical pitch (bit-32) can be set for each row independently - different display modes can be set for each row independently caption text mode / osd mode 1 / osd mode 2 (quarter size) / simplifed graphic mode - ten character sizes *1 horez. vert. = (1 1), (1 2), (2 2), (2 4), (0.5 0.5) (1.5 1), (1.5 2), (3 2), (3 4), (0.75 0.5) - shuttering and scrolling on each row - simplified graphic display *1 note : range depends on display mode : refer to the manual for details. (4) data slicer (ntsc) - line 21 closed caption data and xds data extraction (5) bus cycle time / instruction-cycle time bus cycle time instruction cycle time system clock oscillation oscillation frequency voltage 0.424 s 0.848 s internal vco (ref : x ? tal 32.768khz) 14.156mhz 4.5v to 5.5v 7.5 s 15.0 s internal rc 800khz 4.5v to 5.5v 183.1 s 366.2 s crystal 32.768khz 4.5v to 5.5v (6) ports - input / output ports : 5 ports (28 terminals) data direction programmable in nibble units : 1 port (8 terminals) (if the n-ch open drain output is selected by option, the corresponding port data can be read in output mode.) data direction programmable for each bit individually : 4 ports (20 terminals)
lc863232/28/24/20/16a no.6693-3/20 (7) ad converter - 4 channels 8-bit ad converters (8) serial interfaces - iic-bus compliant serial interface (multi-master type) consists of a single built-in circuit with two i/o channels. the two data lines and two clock lines can be connected internally. - synchronous 8-bit serial interface (9) pwm output - 3 channels 7-bit pwm (10) timer - timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with a programmable prescaler mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter mode 2 : 16-bit timer with a programmable prescaler mode 3 : 16-bit counter the resolution of timer is 1 tcyc. - timer 1 : 16-bit timer/pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable bit pwm (9 to 16 bits) in mode0/1,the resolution of timer1/pwm is 1 tcyc in mode2/3,the resolution is selectable by program; tcyc or 1/2 tcyc - base timer generate every 500ms overflow for a clock application (using 32.768khz crystal oscillation for the base timer clock) generate every 976 s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768khz crystal oscillation for the base timer clock) clock for the base timer is selectable from 32.768khz crystal oscillation, system clock or programmable prescaler output of timer 0 (11) remote control receiver circuit (connected to the p73/int3/t0in terminal) - noise rejection function - polarity switching (12) watchdog timer external rc circuit is required interrupt or system reset is activated when the timer overflows (13) rom correction function max 128 bytes / 2 addresses (14) interrupts - 16 sources 10 vectored interrupts 1. external interrupt int0 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8 bits) 6. timer t1h,t1l 7. sio0 8. data slicer 9. vertical synchronous signal interrupt ( vs ), horizontal line ( hs ), ad 10. iic, port 0
lc863232/28/24/20/16a no.6693-4/20 - interrupt priority control three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. low or high priority can be assigned to the interrupts from 3 to 10 listed above. for the external interrupt int0 and int1, high or highest priority can be set. (15) sub-routine stack level - a maximum of 128 levels (stack is built in the internal ram) (16) multiplication/division instruction - 16 bits 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (17) 3 oscillation circuits - built-in rc oscillation circuit used for the system clock - built-in vco circuit used for the system clock and osd - x ? tal oscillation circuit used for base timer, system clock and pll reference (18) standby function - halt mode the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this mode can be released by the interrupt request or the system reset. - hold mode the hold mode is used to stop the oscillations; rc (internal), vco, and x ? tal oscillations. this mode can be released by the following conditions. pull the reset terminal ( res ) to low level. feed the selected level to either p70/int0 or p71/int1. input the interrupt condition to port 0. (19) package - dip42s - qip48e (20) development tools - flash eeprom: lc86f3248a - evaluation chip: LC863096 - emulator: eva86000 (main) + ecb863200 (evaluation chip board) + pod863200 (pod: dip42s) or pod863201 (qip48e)
lc863232/28/24/20/16a no.6693-5/20 system block diagram interrupt control standby control clock generator x?tal vco rc pll ir pla rom pc acc b register c register alu psw rar ram stack pointer port 0 watch dog timer rom correct control xram bus interface port 1 port 6 port 7 port 8 osd control circuit vram cgrom iic sio0 timer 0 timer 1 base timer adc int0-3 noise rejection filter pwm data slicer
lc863232/28/24/20/16a no.6693-6/20 pin assignment dip42s qip48e p07 p06 p05 p04 p03 p02 p01 p00 p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 i bl b g r p10/so0 p11/si0 p12/sck0 p13/pwm1 p14/pwm2 p15/pwm3 p16 p17/pwm vss xt1 xt2 vdd p84/an4 p85/an5 p86/an6 p87/an7 res filt cvin vs hs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p02 p01 p00 nc p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 nc p14/pwm2 p13/pwm1 p12/sck0 p11/si0 p10/so0 nc p07 p06 p05 p04 p03 res filt cvi n nc vs hs r g b b l i nc p15/pwm3 p16 p17/pwm vss xt1 xt2 vdd nc p84/an4 p85/an5 p86/an6 p87/an7 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 package dimension (unit : mm) 3025b package dimension (unit : mm) 3156 sanyo : dip-42s(600mil) sanyo : qip-48e
lc863232/28/24/20/16a no.6693-7/20 pin description pin description table terminal i/o function description option vss - negative power supply xt1 i input terminal for crystal oscillator xt2 o output terminal for crystal oscillator vdd - positive power supply res i reset terminal filt o filter terminal for pll cvin i video signal input terminal vs i vertical synchronization signal input terminal hs i horizontal synchronization signal input terminal r o red (r) output terminal of rgb image output g o green (g) output terminal of rgb image output b o blue (b) output terminal of rgb image output i o intensity ( i ) output terminal of rgb image output bl o fast blanking control signal switch tv image signal and caption/osd image signal port 0 p00 - p07 i/o 8-bit input/output port, input/output can be specified in nibble unit other functions hold release input interrupt input pull-up resistor provided/not provided output format cmos/nch-od port 1 8-bit input/output port input/output can be specified in a bit other functions p10 p11 p12 p13 p14 p15 p17 sio0 data output sio0 data input/bus input/output sio0 clock input/output pwm1 output pwm2 output pwm3 output timer1 (pwm) output p10 - p17 i/o output format cmos/nch-od port 6 4-bit input/output port input/output can be specified for each bit other functions p60 p61 p62 p63 iic0 data i/o iic0 clock output iic1 data i/o iic1 clock output p60 - p63 i/o
lc863232/28/24/20/16a no.6693-8/20 terminal i/o function description option port 7 4-bit input/output port input or output can be specified for each bit other function p70 p71 p72 p73 int0 input/hold release input/ nch-tr. output for wachdog timer int1 input/hold release input int2 input/timer 0 event input int3 input (noise rejection filter connected)/ timer 0 event input interrupt receiver format, vector addresses rising falling rising/ falling h level l level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h p70 p71 - p73 i/o int3 enable enable enable disable disable 1bh port 8 p84 - p87 i/o 4-bit input/output port input or output can be specified for each bit other function ad converter input port (4 lines) nc - unused terminal leave open output form and existance of pull-up resistor for all ports can be specified for each bit. programmable pull-up resistor is always connected regardless of port option, cmos or n-ch open drain output in port 1. port status in reset terminal i/o pull-up resistor status at selecting pull-up option port 0 i pull-up resistor off, on after reset release port 1 i programmable pull-up resistor off
lc863232/28/24/20/16a no.6693-9/20 1. absolute maximum ratings at vss=0v and ta=25 c ratings parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd -0.3 +7.0 input voltage vi(1) res , hs , vs , cvin -0.3 vdd+0.3 output voltage vo(1) r, g, b, i, bl, filt -0.3 vdd+0.3 input/output voltage vio ports 0, 1, 6, 7, 8 -0.3 vdd+0.3 v ioph(1) ports 0, 1, 7, 8 cmos output for each pin. -4 peak output current ioph(2) r, g, b, i, bl cmos output for each pin. -5 ioah(1) ports 0, 1 the total of all pins. -20 ioah(2) ports 7, 8 the total of all pins. -10 high level output current total output current ioah(3) r, g, b, i, bl the total of all pins. -15 iopl(1) ports 0, 1, 6, 8 for each pin. 20 iopl(2) port 7 for each pin. 15 peak output current iopl(3) r, g, b, i, bl for each pin. 5 ioal(1) ports 0, 1 the total of all pins. 40 ioal(2) ports 6, 7, 8 the total of all pins. 40 low level output current total output current ioal(3) r, g, b, i, bl the total of all pins. 15 ma dip42s 800 maximum power dissipation pdmax qip48e ta=-10 to +70 c 400 mw operating temperature range topr -10 +70 storage temperature range tstg -55 +125 c
lc863232/28/24/20/16a no.6693-10/20 2. recommended operating range at ta=-10 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.844 s t cyc 0.852 s 4.5 5.5 operating supply voltage range vdd(2) vdd 4 s t cyc 400 s 4.5 5.5 hold voltage vhd vdd rams and the registers data are kept in hold mode. 2.0 5.5 vih(1) port 0 (schumitt) output disable 4.5 - 5.5 0.6vdd vdd vih(2) ports 1,6 (schumitt) port 7 (schumitt) port input/interrupt hs , vs , res (schumitt) output disable 4.5 - 5.5 0.75vdd vdd vih(3) port 70 watchdog timer input output disable 4.5 - 5.5 vdd-0.5 vdd high level input voltage vih(4) port 8 port input output disable 4.5 - 5.5 0.7vdd vdd vil(1) port 0 (schumitt) output disable 4.5 - 5.5 vss 0.2vdd vil(2) ports 1,6 (schumitt) port 7 (schumitt) port input/interrupt hs , vs , res (schumitt) output disable 4.5 - 5.5 vss 0.25vdd vil(3) port 70 watchdog timer input output disable 4.5 - 5.5 vss 0.6vdd low level input voltage vil(4) port 8 port input output disable 4.5 - 5.5 vss 0.3vdd v cvin vcvin cvin 5.0 1vp-p -3db 1vp-p 1vp-p +3db vp-p * t cyc (1) all functions operating 4.5 - 5.5 0.844 0.848 0.852 t cyc (2) ad converter operating osd and data slicer are not operating 4.5 - 5.5 0.844 30 operation cycle time t cyc (3) osd, ad converter and data slicer are not operating 4.5 - 5.5 0.844 400 s oscillation frequency range fmrc internal rc oscillation 4.5 - 5.5 0.4 0.8 3.0 mhz * vp-p : peak-to-peak voltage
lc863232/28/24/20/16a no.6693-11/20 3. electrical characteristics at ta=-10 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0, 1, 6, 7, 8 output disable pull-up mos tr. off vin=vdd (including the off- leak current of the output tr.) 4.5 - 5.5 1 high level input current iih(2) res hs , vs vin=vdd 4.5 - 5.5 1 iil(1) ports 0, 1, 6, 7, 8 output disable pull-up mos tr. off vin=vss (including the off- leak current of the output tr.) 4.5 - 5.5 -1 low level input current iil(2) res hs , vs vin=vss 4.5 - 5.5 -1 a voh(1) cmos output of ports 0,1,71-73,8 ioh=-1.0ma 4.5 - 5.5 vdd-1 high level output voltage voh(2) r, g, b, i, bl ioh=-0.1ma 4.5 - 5.5 vdd-0.5 vol(1) ports 0,1,71-73,8 iol=10ma 4.5 - 5.5 1.5 vol(2) ports 0,1,71-73,8 iol=1.6ma 4.5 - 5.5 0.4 vol(3) r, g, b, i, bl port 6 iol=3.0ma 4.5 - 5.5 0.4 vol(4) port 6 iol=6.0ma 4.5 - 5.5 0.6 low level output voltage vol(5) port 70 iol=1ma 4.5 - 5.5 0.4 v pull-up mos tr. resistance rpu ports 0, 1, 7, 8 voh=0.9vdd 4.5 - 5.5 13 38 80 k ? bus terminal short circuit resistance (scl0-scl1, sda0-sda1) rbs p60-p62 p61-p63 4.5 - 5.5 130 ? hysteresis voltage vhis ports 0, 1, 6, 7 res hs , vs output disable 4.5 - 5.5 0.1vdd input clump votage vclmp cvin 5.0 2.3 2.5 2.7 v pin capacitance cp all pins f=1mhz every other terminals are connected to vss. ta=25 c 4.5 - 5.5 10 pf
lc863232/28/24/20/16a no.6693-12/20 4. serial input/output characteristics at ta=-10 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle tckcy(1) 2 low level pulse width tckl(1) 1 input clock high level pulse width tckh(1) sck0 sclk0 refer to figure 4. 4.5 - 5.5 1 cycle tckcy(2) 2 low level pulse width tckl(2) 1/2tckc y serial clock output clock high level pulse width tckh(2) sck0 sclk0 use pull-up resistor (1k ? ) when nch open- drain output. refer to figure 4. 4.5 - 5.5 1/2tckc y tcyc data set up time tick 0.1 serial input data hold time tcki si0 data set-up to sck0. data hold from sck0. refer to figure 4. 4.5 - 5.5 0.1 output delay time (using external clock) tcko(1) so0 4.5 - 5.5 7/12tcyc +0.2 serial output output delay time (using internal clock) tcko(2) so0 data hold from sck0. use pull-up resistor (1k ? ) when nch open- drain output. refer to figure 4. 4.5 - 5.5 1/3tcyc +0.2 s 5. iic input/output conditions at ta=-10 c to +70 c, vss=0v standard high speed parameter symbol min. max. min. max. unit scl frequency fscl 0 100 0 400 khz bus free time between stop - start tbuf 4.7 - 1.3 - s hold time of start, restart condition thd;sta 4.0 - 0.6 - s l time of scl tlow 4.7 - 1.3 - s h time of scl thigh 4.0 - 0.6 - s set-up time of restart condition tsu;sta 4.7 - 0.6 - s hold time of sda thd;dat 0 - 0 0.9 s set-up time of sda tsu;dat 250 - 100 - ns rising time of sda, scl tr - 1000 20+0.1cb 300 ns falling time of sda, scl tf - 300 20+0.1cb 300 ns set-up time of stop condition tsu;sto 4.0 - 0.6 - s refer to figure 10 (note) cb : total capacitance of all bus (unit : pf)
lc863232/28/24/20/16a no.6693-13/20 6. pulse input conditions at ta=-10 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 4.5 - 5.5 1 tpih(2) tpil(2) int3/t0in (1/1 is selected for noise rejection clock.) interrupt acceptable timer0-countable 4.5 - 5.5 2 tpih(3) tpil(3) int3/t0in (1/16 is selected for noise rejection clock.) interrupt acceptable timer0-countable 4.5 - 5.5 32 tpih(4) tpil(4) int3/t0in (1/64 is selected for noise rejection clock.) interrupt acceptable timer0-countable 4.5 - 5.5 128 tcyc tpil(5) res reset acceptable 4.5 - 5.5 200 high/low level pulse width tpih(6) tpil(6) hs , vs display position controllable (note) the active edge of hs and vs must be apart at least 1 tcyc. refer to figure 6. 4.5 - 5.5 8 s rising/falling time tthl ttlh hs refer to figure 6. 4.5 - 5.5 500 ns 7. ad converter characteristics at ta= -10 c to + 70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 8 bit absolute precision et (note 3) 1.5 lsb adcr2=0 (note 4) 16 conversion time tcad adcr2=1 (note 4) 32 tcyc analog input voltage range vain vss vdd v iainh vain=vdd 1 analog port input current iainl an4 - an7 vain=vss 4.5 ? 5.5 -1 a (note 3) absolute precision does not include quantizing error (1/2lsb). (note 4) conversion time is the time till the complete digital conversion value for analog input value is set to a register aft er the instruction to start conversion is sent.
lc863232/28/24/20/16a no.6693-14/20 8. sample current dissipation characteristics at ta= -10 c to +70 c, vss=0v the sample current dissipation characteristics is the measurement result of sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. the currents through the output transistors and the pull-up mos transistors are ignored. ratings parameter symbol pins conditions vdd[v] min. typ. max. unit current dissipation during basic operation (note 3) iddop(1) vdd fmx?tal=32.768khz x?tal oscillation system clock : vco vco for osd operating internal rc oscillation stops 4.5 - 5.5 19 32 ma iddhalt(1) vdd halt mode fmx?tal=32.768khz x?tal oscillation system clock : vco vco for osd stops internal rc oscillation stops 4.5 - 5.5 7 12 ma iddhalt(2) vdd halt mode fmx?tal=32.768khz x?tal oscillation vco for system stops vco for osd stops system clock : internal rc 4.5 - 5.5 300 1200 current dissipation in halt mode (note 3) iddhalt(3) vdd halt mode fmx?tal=32.768khz x?tal oscillation vco for system stops vco for osd stops system clock : x?tal 4.5 - 5.5 50 200 a current dissipation in hold mode (note 3) iddhold vdd hold mode all oscillation stops. 4.5 - 5.5 0.05 20 a (note 3) the currents through the output transistors and the pull-up mos transistors are ignored.
lc863232/28/24/20/16a no.6693-15/20 recommended oscillation circuit and sample characteristics the sample oscillation circuit characteristics in the table below is based on the following conditions: ? recommended circuit parameters are verified by an oscillator manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. recommended oscillation circuit and sample characteristics (ta = -10 to +70 c) recommended circuit parameters oscillation stabilizing time notes frequency manufacturer oscillator c1 c2 rf rd operating supply voltage range typ. max 32.768khz seiko epson c-002rx 18pf 18pf open 390k ? 4.5 ? 5.5v 1.00s 1.50s notes the oscillation stabilizing time period is the time until the vco oscillation for the internal system becomes stable after the following conditions . (refer to figure 2.) 1. the vdd becomes higher than the minimum operating voltage after the power is supplied. 2. the hold mode is released. the sample oscillation circuit characteristics may differ applications. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10 c to +70 c. for the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. ? when using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (xt1 terminal xt2 terminal) and external parts should be as short as possible. ? the capacitors? vss should be allocated close to the microcontroller?s gnd terminal and be away from other gnd. ? the signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. figure 1 recommended oscillation circuit. c1 rd c2 x?tal xt2 xt1 rf
lc863232/28/24/20/16a no.6693-16/20 figure 2 oscillation stabilizing time power supply res internal rc resonato oscillatio n xt1,xt2 vco for system operation mode reset timae vdd vdd limit 0v unfixed instruction execution mode reset tmsvco stable tmsvco stable valid instruction execution mode hold hold release signal xt1,xt2 vco for system operation mode internal rc resonato oscillatio n
lc863232/28/24/20/16a no.6693-17/20 figure 3 reset circuit figure 4 serial input / output test condition (note) determine the cres, rres value to generate more than 200 s reset time. c res vdd r res res so0, so1 sb0, sb1 si0 si1 sck0 sck1 < timing > < t est l oad > 50pf 1k ? v dd t c k o t c ki ti c k t c kh t c kl t c k c y 0.5vdd
lc863232/28/24/20/16a no.6693-18/20 figure 5 pulse input timing condition ? 1 figure 6 pulse input timing condition - 2 figure 7 recommended interface circuit tpih (1)-(4) tpil (1)-(5) tpil(6) tpil(6) ttlh 0.75vdd 0.25vdd more than 1tcyc hs vs lc863232a hs 10k ? c536 hs
lc863232/28/24/20/16a no.6693-19/20 output impedance of c-video before noise filter should be less then 100 ? . figure 8 cvin recommended circuit figure 9 filt recommended circuit (note) place filt parts on board as close to the microcontroller as possible. s : start condition tsp : spike suppression standard mode : not exist p : stop condition high speed mode : less than 50ns sr : restart condition figure 10 iic timing 200 ? c-video 1000pf 1 f cvin noise filter coupling capacitor filt 100 ? 1m ? 2.2 f 33000pf + - sda scl p s sr p tbuf thd;sta tr tlow thd;dat thigh tf tsu;dat tsu;sta thd;sta tsp tsu;sto
lc863232/28/24/20/16a no.6693-20/20 memo: ps

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